Signal Assignments in VHDL (Part 2)

$. Conditional Signal Assignment

Condition Signal allows us to decide when a signal should get updated
Syntax of the Conditional Signal Assignment is

<signal_name>  <= <expression_1> when <condition_1> else
                  <expression_2> when <condition_2> else
                  .
                  .
                  .
                  <expression_n> when <condition_n> else
                  <expression> ;

* <signal_name>   is the name of the signal whose value is to be updated/assigned

* <=                          is the signal assignment operator

* when and else  are the keywords for conditional signal assignment

* <condition_n>   is the condition

* <expression_n> is the expression or value to be assigned to the signal on L.H.S,when its                                                 corresponding condition occurs

* The last expression or value is assigned if none of the condition is satisfied.


Example:

y <= a when s='0' else
     b ;

a,b,s are the input pins/signals
y  is the output pin/signal
All the signals are declared in the entity part of the program

Output signal y is the value of signal a when signal s is 0
As soon as signal s becomes 1, output signal y updates its value to the value of signal b.
Signal a and b can have same or different values,depending on the signal s,y is either equal to a or b.

Previous : Simple Signal Assignment
Next: Selected Signal Assignment

Signal Assignments in VHDL (Part 1)

As Discussed in the previous post,there are three different types of Signal Assignments-
1. Simple Signal Assignment
2. Conditional Signal Assignment
3. Selected Signal Assignment

Syntax's of each type of signal assignments are given as --

$. Simple Signal Assignment



<signal_name> <= <expression> ;

* <signal_name>  is the name of signal to which a value or an expression is to be assigned

* <=                          is the signal assignment operator
                                     Note that it is an <= and not just an equal to sign =

* <expression>     is the expression or a value
                                  As soon as some value in an expression changes an implicit process is
                                  called and the new value is assigned to the signal

Example:

c <= a xor b 

a,b are the input pins/signals
c is the output pin/signal
a,b and c are declared in entity part of the program

Signal c is the logical xor of signal a and signal b

If either or both of input signals a or b change their value, signal c changes accordingly.


Previous : Fundamentals of writing an architecture in VHDL
Next : Conditional Signal Assignment 

Fundamentals of writing an Architecture in VHDL

The basic aim of an Architecture is to obtain an output signal/s when input signal/s are applied.
It generates an output signal on the output pin (a pin which can write to) based on the input signals applied on the input pin (a pin which can be read from). The input and output pin/ports are declared in the entity part of the program.
Thus the code written inside Architecture specifies the logical relation between input and output.

An Architecture is modeled with the use of -
* Signals,variables,user defined types and operators
* Signal assignment statements
* Processes

$. Signal Assignment Statements (Implicit Process)

Signal assignment implies a process(function) that is executed in parallel when anything on the right hand side of the assignment changes.

Three types of Signal Assignment Statements are -
* Simple Signal Assignment
* Conditional Signal Assignment (When else statements)
* Selected Signal Assignment (With select statements)

$. Process

A process in VHDL architecture is a set of statements that are executed sequentially and not in parallel.
A process can be declared explicitly and the sequential statements that can be used inside a process are -
* Simple Signal Assignment
* If-Then Statements
* Case Statements
* Looping Statements
* Wait Statements


Previous: Getting started with VHDL
Next : Signal Assignments in VHDL (Part 1)

Getting Started with VHDL

A VHDL program consists of 4 Main Design Units

1.Entity
-It is how the system is viewed externally

2.Architecture
-It is a description of functionality (Schematic)

3.Configuration
-It assosciates Entity and Architecture

4.Package
-It is used to store a Reusable code(Library)



$. ENTITY DECLARATION SYNTAX :
 

Entity <name_of_entity> is

Generic Declarations

Port Declarations

end <name_of_entity>;

*  <name_of_entity> is any alphanumeric name given to the entity

*  Generic Declarations are used to pass information into a model

*  Port Declarations are used to describe the input,output pins



$. Port Declaration Syntax:
 

Port(
port_name1:<mode> <type> ;
port_name2:<mode> <type> ;
.
.
.
port_nameN:<mode> <type> 
);



* port_name is a name given to the port/pin

* <mode> is used to specify the direction of data flow through that pin,
                   modes are-
in         -for input
                  input signals can only be read from
out          -for output
           output signals can only be written to
inout     -bidirectional
buffer -output with internal feedback
          physically it is an output pin but can also be read

* <type> is used to specify the data type of the port
            Some of the commonly used types are-
  STD_LOGIC - Declares a Standard Logic Bit which can have values
                     0 (logic low)
                     1 (logic high)
              x (Unknown)
                     z (Tristate)
                     - (Don't Care)

  STD_LOGIC_VECTOR(m downto 0) - Declares a Standard Logic Vector of m+1 bits                    where port_name(m) signifies the MSB and port_name(0) signifies the LSB.

Note that Every port declaration ends with a semi-colon except the last one


$. ARCHITECTURE :
 
Architecture describes the internal logic of our model,the outside world can only see the port connections and the parameters passed to it.
Note: An architecture must be associated to an Entity
  Entity can have multiple architecture.


Syntax of Architecture:



Architecture <identifier> of <name_of_entity> is

Declaration of variables that aren't ports or generics

Begin
.
.
.
Body of Architecture 
.
.
.
End Architecture <identifier> ;

* <identifier> is the name given to the architecture
* Variables that aren't ports or generics are declared before Begin
   these variables are generally Temporary Signals or Constants for interconnections.
* Body of Architecture is the description of functionality and timing of the model.
    It consists of executable statements


Next : Fundamentals of  writing an architecture in VHDL