Process Statements in VHDL (Explicit Signal Assignments)

Signal assignments that we have seen so far were Implicit,that is they were executed any time. Whenever the signal on their right hand side changed the value of signal on the left hand side was updated.

We use a Process in VHDL to execute the statements in sequence.Along with the Explicit signal assignments it can also consist of the Simple signal assignment statements we have seen so far.

The Syntax of using a process is as follows :

Process (Sensitivity_List)

Constant declarations
Type declarations
Variable declarations

Begin
         Sequential Statement 1;
         Sequential Statement 2;
         .
         .
         .
         .
         Sequential Statement n;
End Process

* Process is the keyword declaring the process

* Sensitivity_List is a list of inputs that a process would require

* All the local variables that are needed are declared between the Process and Begin statement

* The actual function of the process is written between the Begin and End Process statements

Previous : Selected signal assignment
Next: Sequential Statements

Signal Assignments in VHDL (Part 3)

$. Selected Signal Assignment

Syntax of Selected Signal Assignment is

with <select_sig_expression> select
<signal_name>  <= <expression_1> when <condition_1> ,
                  <expression_2> when <condition_2> ,
                  .
                  .
                  .
                  <expression_n> when others       ;


* <signal_name>   is the name of the signal whose value is to be updated/assigned

* <=                          is the signal assignment operator

* with,select and when  are the keywords for selected signal assignment

* <select_sig_expression> is the signal/expression that is monitored for the change of condition

* <condition_n>   is the condition

* <expression_n> is the expression or value to be assigned to the signal on L.H.S,when its                                                 corresponding condition occurs

* when others  implies condition/s apart from the ones that are mentioned
   Thus the expression or value corresponding to 'when others' is assigned if none of the condition          mentioned are satisfied.



Example:

with sel select

y <= a when "00"
     b when "01"
     c when "10"
     d when others ;

a,b,c,d,sel are the input pins/signals
y  is the output pin/signal
All the signals are declared in the entity part of the program

Output signal y depends on the value of sel signal,
That is the Output signal y is the value of signal a when signal sel is 00, it is the value of signal b when signal sel is 01,it is the value of signal c when signal sel is 10 and it outputs the value of signal d when sel is neither equal to any of the values mentioned.

As signal sel changes, output signal y updates its value to the value of signal a,b,c or d.

Previous : Conditional Signal Assignment
Next: Explicit Process Statements