Process Statements in VHDL (Explicit Signal Assignments)

Signal assignments that we have seen so far were Implicit,that is they were executed any time. Whenever the signal on their right hand side changed the value of signal on the left hand side was updated.

We use a Process in VHDL to execute the statements in sequence.Along with the Explicit signal assignments it can also consist of the Simple signal assignment statements we have seen so far.

The Syntax of using a process is as follows :

Process (Sensitivity_List)

Constant declarations
Type declarations
Variable declarations

Begin
         Sequential Statement 1;
         Sequential Statement 2;
         .
         .
         .
         .
         Sequential Statement n;
End Process

* Process is the keyword declaring the process

* Sensitivity_List is a list of inputs that a process would require

* All the local variables that are needed are declared between the Process and Begin statement

* The actual function of the process is written between the Begin and End Process statements

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