Signal Assignments in VHDL (Part 2)

$. Conditional Signal Assignment

Condition Signal allows us to decide when a signal should get updated
Syntax of the Conditional Signal Assignment is

<signal_name>  <= <expression_1> when <condition_1> else
                  <expression_2> when <condition_2> else
                  .
                  .
                  .
                  <expression_n> when <condition_n> else
                  <expression> ;

* <signal_name>   is the name of the signal whose value is to be updated/assigned

* <=                          is the signal assignment operator

* when and else  are the keywords for conditional signal assignment

* <condition_n>   is the condition

* <expression_n> is the expression or value to be assigned to the signal on L.H.S,when its                                                 corresponding condition occurs

* The last expression or value is assigned if none of the condition is satisfied.


Example:

y <= a when s='0' else
     b ;

a,b,s are the input pins/signals
y  is the output pin/signal
All the signals are declared in the entity part of the program

Output signal y is the value of signal a when signal s is 0
As soon as signal s becomes 1, output signal y updates its value to the value of signal b.
Signal a and b can have same or different values,depending on the signal s,y is either equal to a or b.

Previous : Simple Signal Assignment
Next: Selected Signal Assignment