Signal Assignments in VHDL (Part 1)

As Discussed in the previous post,there are three different types of Signal Assignments-
1. Simple Signal Assignment
2. Conditional Signal Assignment
3. Selected Signal Assignment

Syntax's of each type of signal assignments are given as --

$. Simple Signal Assignment



<signal_name> <= <expression> ;

* <signal_name>  is the name of signal to which a value or an expression is to be assigned

* <=                          is the signal assignment operator
                                     Note that it is an <= and not just an equal to sign =

* <expression>     is the expression or a value
                                  As soon as some value in an expression changes an implicit process is
                                  called and the new value is assigned to the signal

Example:

c <= a xor b 

a,b are the input pins/signals
c is the output pin/signal
a,b and c are declared in entity part of the program

Signal c is the logical xor of signal a and signal b

If either or both of input signals a or b change their value, signal c changes accordingly.


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